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ltc4215/ltc4215-2 1 4215fe typical application description hot swap controller with i 2 c compatible monitoring the ltc ? 4215/ltc4215-2 hot swap? controllers allow a board to be safely inserted and removed from a live backplane. using an external n-channel pass transistor, board supply voltage and inrush current are ramped up at an adjustable rate. an i 2 c interface and onboard adc allow for monitoring of load current, voltage and fault status. the device features adjustable foldback current limit and a soft-start pin that sets the di/dt of the inrush current. an i 2 c interface may con? gure the part to latch off or automatically restart after the ltc4215 detects a current limit fault. the controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card, and power-up either automatically upon insertion or wait for an i 2 c command to turn on. the ltc4215 has a 20s circuit breaker ? lter for applica- tions that require a fast fault response time and it defaults to latchoff after an overcurrent fault. the ltc4215-2 has an extended 420s circuit breaker ? lter for applications where supply transients may exceed 20s and it defaults to restart automatically after an overcurrent fault. features applications n live board insertion n electronic circuit breakers n computers, servers n platform management n allows safe insertion into live backplane n 8-bit adc monitors current and voltage n i 2 c/smbus interface n wide operating voltage range: 2.9v to 15v n 20s (ltc4215) or 420s (ltc4215-2) circuit breaker timeout n di/dt controlled soft-start n high side drive for external n-channel mosfet n no external gate capacitor required n input overvoltage/undervoltage protection n optional latchoff or auto-retry after faults n alerts host after faults n inrush current limit with foldback n available in 24-pin (4mm 5mm) qfn package n ltc4215 also available in 16-lead narrow ssop package + uv v dd sense + sense C ltc4215ufd gate timer ss on gnd source ov sdao sdai scl alert intv cc fb en adin gpio 3.4k plug-in card 1.18k p6ke16a 10 0.005 fdc653n 30.1k v out 12v 3.57k 24k 4215 ta01a c l intv cc intv cc 0.1f connector 2 connector 1 0.1f 34.8k backplane 68nf gnd alert scl sda 12v v out 10v/div v gpio (powergood) 10v/div inrush current 2.5a/div v dd 10v/div 50ms/div 42151 ta01b c l = 12000f contact bounce 12v application with 5a circuit breaker start-up waveform l , lt, ltc, ltm, linear technology, the linear logo and hot swap are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patent including 7330065.
ltc4215/ltc4215-2 2 4215fe absolute maximum ratings supply voltage (v dd ) ................................ C0.3v to 24v supply voltage (intv cc ) .......................... C0.3v to 6.5v input voltages gate-source (note 3) .......................... C0.3v to 5v sense + , sense C ................ v dd C 0.3v to v dd + 0.3v source .................................................... C5v to 24v en , fb, on, ov, uv ................................ C0.3v to 12v adr0, adr1, adr2, timer, adin, ss ................................ C0.3v to intv cc + 0.3v alert scl, sda, sdai, sdao ............. C0.3v to 6.5v order information lead free finish tape and reel part marking* package description temperature range ltc4215cgn#pbf ltc4215cgn#trpbf 4215 16-lead plastic tssop 0c to 70c ltc4215ign#pbf ltc4215ign#trpbf 4215i 16-lead plastic tssop C40c to 85c ltc4215cufd#pbf ltc4215cufd#trpbf 4215 24-lead (4mm 5mm) plastic qfn 0c to 70c ltc4215iufd#pbf ltc4215iufd#trpbf 4215 24-lead (4mm 5mm) plastic qfn C40c to 85c ltc4215cufd-2#pbf ltc4215cufd-2#trpbf 42152 24-lead (4mm 5mm) plastic qfn 0c to 70c ltc4215iufd-2#pbf ltc4215iufd-2#trpbf 42152 24-lead (4mm 5mm) plastic qfn C40c to 85c pin configuration (notes 1, 2) output voltages gate, gpio ............................................ C0.3v to 24v operating temperature range ltc4215c ................................................ 0c to 70c ltc4215i.............................................. C40c to 85c storage temperature range ssop ................................................. C65c to 150c qfn .................................................... C65c to 125c lead temperature (soldering, 10 sec) ssop ................................................................ 300c ltc4215 ltc4215/ltc4215-2 gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 sense C v dd uv ss gnd on sda scl gate source fb gpio intv cc timer adr0 alert t jmax = 125c, ja = 130c/w 8 9 top view 25 ufd package 24-lead (4mm s 5mm) plastic qfn 10 11 12 24 23 22 21 20 6 5 4 3 2 1 uv ov ss gnd on en sdao fb gpio intv cc timer adin adr2 adr1 v dd sense + sense C gate source sdai scl alert nc adr0 7 14 15 16 17 18 19 13 t jmax = 125c, ja = 43c/w exposed pad (pin 25) not guaranteed low impedance to gnd, electrical connection optional
ltc4215/ltc4215-2 3 4215fe electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. symbol parameter conditions min typ max units supplies v dd input supply range l 2.9 15 v v ov(vdd) input supply overvoltage threshold l 15 15.6 16.5 v i dd input supply current l 35 ma v dd(uvl) input supply undervoltage lockout v dd rising l 2.75 2.84 2.89 v v dd(hyst) input supply undervoltage lockout hysteresis l 75 100 125 mv intv cc internal regulator voltage v dd 3.3v l 2.9 3.1 3.4 v intv cc(uvl) intv cc undervoltage lockout intv cc rising l 2.55 2.64 2.79 v intv cc(hyst) intv cc undervoltage lockout hysteresis l 20 55 75 mv current limit and circuit breaker v sense(th) circuit breaker threshold (v dd C v sense ) l 22.5 25 27.5 mv v sense current limit voltage (v dd C v sense )v fb = 1.3v v fb = 0v start-up timer expired l l l 22 6.5 65 25 10 75 29 13 90 mv mv mv t d(oc) oc fault filter v sense = 50mv, ltc4215 v sense = 50mv, ltc4215-2 l l 15 300 20 420 30 600 s s i sense(in) sense + /C input current v sense = 12v l 10 20 35 a gate drive v gate external n-channel gate drive (v gate C v source ) (note 3) v dd = 2.9v to 15v l 4.7 5.9 6.5 v i gate(up) external n-channel gate pull-up current gate on, v gate = 0v l C15 C20 C30 a i gate(dn)slow external n-channel gate pulldown current gate off, v gate = 15v l 0.8 1 1.6 ma i gate(dn)fast pulldown current from gate to source during oc/uvlo v dd C sense = 100mv, v gs = 4v l 300 450 700 ma t phl(sense) (v dd C sense) high to gate low v dd C sense = 100mv, c gs = 10nf l 0.5 1 s v gs(powerbad) gate-source voltage for power bad fault v source = 2.9v C 15v l 3.8 4.3 4.7 v order information lead based finish tape and reel part marking* package description temperature range ltc4215cgn ltc4215cgn#tr 4215 16-lead plastic tssop 0c to 70c ltc4215ign ltc4215ign#tr 4215i 16-lead plastic tssop C40c to 85c ltc4215cufd ltc4215cufd#tr 4215 24-lead (4mm 5mm) plastic qfn 0c to 70c ltc4215iufd ltc4215iufd#tr 4215 24-lead (4mm 5mm) plastic qfn C40c to 85c ltc4215cufd-2 ltc4215cufd-2#tr 42152 24-lead (4mm 5mm) plastic qfn 0c to 70c ltc4215iufd-2 ltc4215iufd-2#tr 42152 24-lead (4mm 5mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc4215/ltc4215-2 4 4215fe electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. symbol parameter conditions min typ max units comparator inputs v on(th) on pin threshold voltage v on rising l 1.210 1.235 1.26 v v on(hyst) on pin hysteresis l 60 128 180 mv i on(in) on pin input current v on = 1.2v l 0 1 a v en (th) en input threshold v en = rising l 1.215 1.235 1.255 v v en (hyst) en hysteresis l 50 128 200 mv i en en pin input current en = 3.5v l 0 1 a v ov(th) ov pin threshold voltage v ov rising l 1.215 1.235 1.255 v v ov(hyst) ov pin hysteresis l 10 30 40 mv i ov(in) ov pin input current v ov = 1.8v l 0 1 a v uv(th) uv pin threshold voltage v uv rising l 1.215 1.235 1.255 v v uv(hyst) uv pin hysteresis l 60 80 100 mv i uv(in) uv pin input current v uv = 1.8v l 0 1 a v uv(rth) uv pin reset threshold voltage v uv falling l 0.33 0.4 0.47 v v uv(rhyst) uv pin reset threshold hysteresis l 60 125 210 mv v fb foldback pin power good threshold fb rising l 1.215 1.235 1.255 v v fb(hyst) fb pin power good hysteresis l 3815 mv i fb foldback pin input current fb = 1.8v l 0 1 a v gpio(th) gpio pin input threshold v gpio rising l 0.8 1 1.2 v other pin functions v gpio(ol) gpio pin output low voltage i gpio = 5ma l 0.25 0.5 v i gpio(oh) gpio pin input leakage current v gpio = 15v l 0 1 a i source source pin input current source = 15v l 40 80 120 a t p(gate) input (on, ov, uv, en) to gate off propagation delay l 35 s t d(gate) turn-on delay on uv, ov, en overcurrent auto-retry l l l 50 2.5 1 100 5 2 150 75 s ms s v timerl(th) timer low threshold l 0.17 0.2 0.23 v v timerh(th) timer high threshold l 1.2 1.235 1.26 v i timer(up) timer pin pull-up current l C80 C100 C120 a i timer(down) timer pin pulldown current for oc auto-retry l 1.4 2 2.6 a i timer(up/down) timer current up/down ratio l 40 50 60 i ss soft-start ramp pull-up current ramping waiting for gate to slew l l C7.5 C0.4 C10 C0.7 C12.5 C1.0 a a adc res resolution (no missing codes) l 8 bits inl integral nonlinearity v dd C sense (note 5) source adin l l l C2 C1.25 C1.25 0.5 0.2 0.2 2 1.25 1.25 lsb lsb lsb v os offset error (note 4) v dd C sense source adin l l l 2.0 1.0 1.0 lsb lsb lsb
ltc4215/ltc4215-2 5 4215fe electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise speci? ed. note 3: an internal clamp limits the gate pin to a minimum of 5v above source. driving this pin to voltages beyond the clamp may damage the device. note 4: offset error is the offset voltage measured from 1lsb when the output code ? ickers between 0000 0000 and 0000 0001. note 5: integral nonlinearity is de? ned as the deviation of a code from a precise analog input voltage. maximum speci? cations are limited by the lsb step size and the single shot measurement. typical speci? cations are measured from the 1/4, 1/2 and 3/4 areas of the quantization band. note 6: guaranteed by design and not subject to test. symbol parameter conditions min typ max units tue total unadjusted error v dd C sense source adin l l l 5.5 5.0 5.0 lsb lsb lsb fse full-scale error v dd C sense source adin l l l 5.5 5.0 5.0 lsb lsb lsb v fs full-scale voltage (255 ? v lsb )v dd C sense source adin l l l 37.625 15.14 1.205 38.45 15.44 1.23 39.275 15.74 1.255 mv v v r adin adin pin sampling resistance v adin = 1.28v l 12 m i adin adin pin input current v adin = 1.28v l 0 0.1 a conversion rate 10 hz i 2 c interface v adr(h) adr0, adr1, adr2 input high voltage l intv cc C0.8 intv cc C0.4 intv cc C0.2 v i adr(in,z) adr0, adr1, adr2 hi-z input current adr0, adr1, adr2 = 0.8v adr0, adr1, adr2 = intv cc C 0.8v l l 3 C3 a a v adr(l) adr0, adr1, adr2 input low voltage l 0.2 0.4 0.8 v i adr(in) adr0, adr1, adr2 input current adr0, adr1, adr2 = 0v, intv cc l C80 80 a i alert alert input current alert = 6.5v l 1 a v alert( ol) alert output low voltage i alert = 3ma l 0.2 0.4 v v sda,scl(th) sda, scl input threshold l 1.3 1.7 1.9 v i sda,scl(oh) sda, scl input current scl, sda = 6.5v l 1 a v sda(ol) sda output low voltage i sda = 3ma l 0.2 0.4 v i 2 c interface timing f scl(max) scl clock frequency operates with f scl f scl(max) l 400 1000 khz t buf(min) bus free time between stop/start condition l 0.12 1.3 s t hd,sta(min) hold time after (repeated) start condition l 30 600 ns t su,sta(min) repeated start condition set-up time l 30 600 ns t su,sto(min) stop condition set-up time l 140 600 ns t hd,dat(min) data hold time (input) l 30 100 ns t hd,dato data hold time (output) l 300 500 900 ns t su,dat(min) data set-up time l 30 600 ns t sp suppressed spike pulse width l 50 110 250 ns c x scl, sda input capacitance sdai tied to sdao (note 6) l 10 pf
ltc4215/ltc4215-2 6 4215fe typical performance characteristics temperature (c) C50 C25 1.230 v th (uv) rising (v) 1.234 1.240 0 50 4215 g04 1.232 1.238 1.236 25 75 100 temperature (c) C50 C25 70 75 80 85 v hyst(uv) (mv) 90 0 50 4215 g05 25 75 100 temperature (c) C50 C25 90 i timer (a) 110 0 50 4215 g06 95 105 100 25 75 100 v fb (v) 0 i lim (mv) 20 25 30 1.2 1.4 4215 g07 15 10 0 0.2 0.4 0.6 0.8 1.0 5 temperature (c) C50 C25 22 circuit breaker threshold (mv) 24 27 0 50 75 4215 g08 23 26 25 25 100 v dd = 5v, 12v v dd = 3.3v current limit vs v fb v th circuit breaker vs temperature v th(uv) vs temperature v hyst(uv) vs temperature i timer vs temperature t a = 25c, v dd = 12v unless otherwise noted v (sense+) C v (senseC) (mv) 0 25 50 75 100 125 150 t phl v (gate) (s) 1 100 4215 g17 10 0.1 t phl(gate) vs sense voltage v dd (v) 0 0 i dd (ma) 2 4 5 4215 g01 1 3 10 25 15 20 intv cc (v) 2.5 v dd (v) 2.5 3.0 4.0 4215 g02 3.0 3.5 4.0 3.5 i load (ma) 0 0 v cc (v) 2 4 4215 g03 1 3 4 10 2 68 v dd = 12v, 5v v dd = 3.3v i dd vs v dd intv cc vs v dd intv cc vs i load
ltc4215/ltc4215-2 7 4215fe temperature (c) C50 v gate(source) (v) 5.8 5.9 6.0 75 4215 g09 5.7 5.6 C25 25 0 50 100 5.5 5.4 6.1 v dd = 3.3v v dd = 12v v dd = 5v i gate (a) 0 5 6 7 20 4215 g10 4 3 51015 25 2 1 0 v gate (v) v dd = 3.3v v dd = 12v v dd = 5v temperature (c) C50 C10 i gate (a) C20 C30 C25 0 50 75 4315 g11 C15 C25 25 100 i gpio1 (ma) 0 v ol(gpio1) (v) 0.2 0.4 0.6 0.1 0.3 0.5 2468 4215 g12 10 0 v dd = 3.3v, 5v, 12v typical performance characteristics v gate vs temperature v gate vs i gate i gate pull-up vs temperature v ol(gpio) vs i gpio t a = 25c, v dd = 12v unless otherwise noted code 0 64 128 192 0 0.001 0.002 0.003 0.004 0.006 4215 g13 256 0.005 error (mv) code 0 inl (lsb) 128 192 4215 g14 256 64 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 temperature (c) C50 C25 C1.0 full-scale error (lsb) C0.2 1.0 0 50 4215 g05 C0.6 0.6 0.2 C0.4 0.8 C0.8 0.4 0 25 75 100 code 0 C0.5 C0.4 C0.3 dnl (lsb) C0.1 C0.2 0 0.1 0.2 0.5 0.4 128 4215 g15 256 64 192 0.3 total unadjusted error vs code (adin) adc inl vs code (adin) adc dnl vs code (adin) adc full-scale error vs temperature
ltc4215/ltc4215-2 8 4215fe pin functions adin (qfn package): adc input. a voltage between 0v and 1.235v applied to this pin is measured by the onboard adc. tie to ground if unused. adr0, adr1, adr2 (adr1, adr2 available in qfn pack- age): serial bus address inputs. tying these pins to ground, to the intv cc pin or open con? gures one of 27 possible addresses. see table 1 in applications information. alert : fault alert output. open-drain logic output that is pulled to ground when a fault occurs to alert the host controller. a fault alert is enabled by the alert register. see applications information. tie to ground if unused. en (qfn package): enable input. ground this pin to indicate a board is present and enable the n-channel mosfet to turn on. when this pin is high, the mosfet is not allowed to turn on. an internal 10a current source pulls up this pin. transitions on this pin are recorded in the fault register. a high-to-low transition activates the logic to read the state of the on pin and clear faults. see applications information. exposed pad (pin 25, qfn package): exposed pad may be left open or connected to device ground. fb: foldback current limit and power good input. a resistive divider from the output is tied to this pin. when the voltage at this pin drops below 1.235v, power is not considered good. the power bad condition may result in the gpio pin pulling low or going high impedance depending on the con? guration of control register bits a6 and a7. also a power bad fault is logged in this condition if the ltc4215 has ? nished the start-up cycle and the gate pin is high. see applications information. the start-up current limit folds back from a 25mv sense voltage to 10mv as the fb pin voltage falls from 0.6v to 0v. foldback is not active once the part leaves start-up and the current limit is increased to 75mv. gate: gate drive for external n-channel mosfet. an internal 20a current source charges the gate of the mosfet. often no compensation capacitor is required on the gate pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output voltage slew rate. see applications information. during turn-off there is a 1ma pulldown current. during a short circuit or undervoltage lockout (v dd or intv cc ), a 450ma pulldown current source between gate and source is activated. gnd: device ground. gpio: general purpose input/output. open-drain logic output or logic input. defaults to an output set to pull low to indicate power is not good. con? gure according to table 2 and 3. intv cc : low voltage supply decoupling output. connect a 0.1f capacitor from this pin to ground. on: on control input. a rising edge turns on the external n-channel mosfet and a falling edge turns it off. this pin also con? gures the state of the fet on bit in the con- trol register (and hence the external mosfet) at power up. for example, if the on pin is tied high, then the fet on bit (a3 in table 2) goes high 100ms after power-up. likewise if the on pin is tied low then the part remains off after power-up until the fet on bit is set high using the i 2 c bus. a high-to-low transition on this pin clears the fault register. ov (qfn package): overvoltage comparator input. con- nect this pin to an external resistive divider from v dd . if the voltage at this pin rises above 1.235v, an overvoltage fault is detected and the gate turns off. tie to gnd if unused.
ltc4215/ltc4215-2 9 4215fe pin functions scl: serial bus clock input. data at the sda pin is shifted in or out on rising edges of scl. this is a high impedance pin that is generally driven by an open-collector output from a master controller. an external pull-up resistor or current source is required. sdao (qfn package): serial bus data output. open-drain output for sending data back to the master controller or acknowledging a write operation. normally tied to sdai to form the sda line. an external pull-up resistor or cur- rent source is required. internally tied to sdai in ssop package. sdai: serial bus data input. a high impedance input for shifting in address, command or data bits. normally tied to sdao to form the sda line. internally tied to sdao in ssop package. sda (ssop package): serial bus data input/output line. formed by internally tying the sdao and sdai lines to- gether. an external pull-up resistor or current source is required. sense + (qfn package): positive current sense input. connect this pin to the input of the current sense resistor. must be connected to the same trace as v dd . internally tied to v dd in ssop package. sense C : negative current sense input. connect this pin to the output of the current sense resistor. this pin provides sense voltage feedback and monitoring for the current limit, circuit breaker and adc. source: n-channel mosfet source and adc input. connect this pin to the source of the external n-channel mosfet switch for gate drive return. this pin also serves as the adc input to monitor output voltage. the pin provides a return for the gate pulldown circuit. ss: soft start input. sets the inrush current slew rate at start-up. connect a 68nf capacitor to provide 5mv/ms as the slew rate for the sense voltage in start-up. this cor- responds to 1a/ms with a 5m sense resistor. note that a large soft-start capacitor and a small timer capacitor may result in a condition where the timer expires before the inrush current has started. allow an additional 10nf of timer capacitance per 1nf of soft-start capacitor to ensure proper start-up. use 1nf minimum to ensure an accurate inrush current. timer: start-up timer input. connect a capacitor be- tween this pin and ground to set a 12.3ms/f duration for start-up, after which an overcurrent fault is logged if the inrush is still current limited. the duration of the off time is 600ms/f when overcurrent auto-retry is enabled, resulting in a 1:50 duty cycle. an internal timer provides a 100ms start-up time and 5 seconds auto-retry time if this pin is tied to intv cc . allow an additional 10nf of timer capacitance per 1nf of soft-start (ss) capacitor to ensure proper start-up. the minimum value for the timer capacitor is 10nf. uv: undervoltage comparator input. connect this pin to an external resistive divider from v dd . if the voltage at this pin falls below 1.155v, an undervoltage fault is detected and the gate turns off. pulling this pin below 0.4v resets all faults and allows the gate to turn back on. tie to intv cc if unused. v dd : supply voltage input. this pin has an undervoltage lockout threshold of 2.84v and overvoltage lockout threshold of 15.6v.
ltc4215/ltc4215-2 10 4215fe timing diagram t su, dat t su, sto t su, sta t buf t hd, sta t sp t sp t hd, dato, t hd, dati t hd, sta start condition stop condition repeated start condition start condition 4215 td01 sdai/sdao scl functional diagram 1.235v + C + C + C + C + C + C + C + C + C uv uv + C + C + C pg pwrgd fault cb 25mv 75mv cs gate source fet on sense C sense + (qfn) foldback and di/dt rst uv fb on v dd adin (qfn) sdai (qfn) sdao (qfn) scl alert ov (qfn) en (qfn) 0.4v 1.235v 10a intv cc 10a v cc 1.235v 1.235v 2.84v 15.6v 1.235v ss 1.235v 0.6v reset ov1 ov en en on tm1 gp uvlo2 tm2 on ov2 ov2 uvlo1 v dd(uvlo) charge pump and gate driver gpi0 1v timer + C 0.2v 1.235v v dd C v sense i 2 c addr source a/d converter 8 100a 2.64v 3.1v gen 2a + C + C adro adr1 (qfn) 4215 bd adr2 (qfn) intv cc + C 5 sda (ssop) i 2 c 1 of 27 logic
ltc4215/ltc4215-2 11 4215fe the ltc4215 is designed to turn a boards supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. during normal operation, the charge pump and gate driver turn on an external n-channel mosfets gate to pass power to the load. the gate driver uses a charge pump that derives its power from the v dd pin. also included in the gate driver is an internal 6.5v gate-to-source clamp. during start-up the inrush current is tightly controlled by using current limit foldback, soft start di/dt limiting and output dv/dt limiting. the current sense (cs) ampli? er monitors the load current using the difference between the sense + (v dd for ssop) and sense C pin voltages. the cs ampli? er limits the cur- rent in the load by pulling back on the gate-to-source voltage in an active control loop when the sense voltage exceeds the commanded value. the cs ampli? er requires 20a input bias current from both the sense + and the sense C pins. a short circuit on the output to ground results in excessive power dissipation during active current limiting. to limit this power, the cs ampli? er regulates the voltage between the sense + and sense C pins at 75mv. if an overcurrent condition persists, the internal circuit breaker (cb) registers a fault when the sense voltage ex- ceeds 25mv for more than 20s in the case of the ltc4215 or 420s in the case of the ltc4215-2. this indicates to the logic that it is time to turn off the gate to prevent overheating. at this point the start-up timer pin voltage ramps down using the 2a current source until the volt- age drops below 0.2v (comparator tm1) which tells the logic that the pass transistor has cooled and it is safe to turn it on again if overcurrent auto-retry is enabled. if the timer pin is tied to intv cc , the cool-down time defaults to 5 seconds on an internal system timer in the logic. the output voltage is monitored using the fb pin and the power good (pg) comparator to determine if the power is available for the load. the power good condition can be signaled by the gpio pin using an open-drain pulldown transistor. the gpio pin may also be con? gured to signal power bad, or as a general purpose input (gp comparator), or a general purpose open drain output. the functional diagram shows the monitoring blocks of the ltc4215. the group of comparators on the left side includes the undervoltage (uv), overvoltage (ov), reset (rst), enable ( en ) and signal on (on) comparators. these comparators determine if the external conditions are valid prior to turning on the gate. but ? rst the two undervoltage lockout circuits, uvlo1 and uvlo2, validate the input supply and the internally generated 3.1v supply, intv cc . uvlo2 also generates the power-up initialization to the logic circuits as intv cc crosses this rising threshold. if the ? xed internal overvoltage comparator, ov2, detects that v dd is greater than 15.6v, the part immediately generates an overvoltage fault and turns the gate off. included in the ltc4215 is an 8-bit a/d converter. the con- verter has a 3-input multiplexer to select between the adin pin, the source pin and the v dd C sense voltage. an i 2 c interface is provided to read the a/d registers. it also allows the host to poll the device and determine if faults have occurred. if the alert line is con? gured as an interrupt, the host is enabled to respond to faults in real time. the typical sda line is divided into an sdai (input) and sdao (output). this simpli? es applications using an optoisolator driven directly from the sdao output. an ap- plication which uses optoisolation is shown in figure 14. the i 2 c device address is decoded using the adr0, adr1 and adr2 pins. these inputs have three states each that decode into a total of 27 device addresses. adr1 and adr2 are not available in the ssop package; therefore, those pins are nc in the address map. operation
ltc4215/ltc4215-2 12 4215fe applications information a typical ltc4215 application is in a high availability system in which a positive voltage supply is distributed to power individual cards. the device measures card voltages and currents and records past and present fault conditions. the system queries each ltc4215 over the i 2 c periodically and reads status and measurement information. a basic ltc4215 application circuit is shown in figure 1. the following sections cover turn-on, turn-off and various faults that the ltc4215 detects and acts upon. external component selection is discussed in detail in the design example section. turn-on sequence the power supply on a board is controlled by using an external n-channel pass transistor (q1) placed in the power path. note that resistor r s provides current detection. re- sistors r1, r2 and r3 de? ne undervoltage and overvoltage levels. r5 prevents high frequency oscillations in q1 and r6 and c1 form an optional network that may be used to provide an output dv/dt limited start-up. several conditions must be present before the external mosfet turns on. first the external supply, v dd , must exceed its 2.84v undervoltage lockout level. next the internally generated supply, intv cc , must cross its 2.64v undervoltage threshold. this generates a 60s to 120s power-on-reset pulse. during reset the fault registers are cleared and the control registers are set or cleared as described in the register section. after a power-on-reset pulse, the ltc4215 goes through the following turn-on sequence. first the uv and ov pins indicate that input power is within the acceptable range, which is indicated by bits c0-c1 in table 4. second, the en pin is externally pulled low. finally, all of these conditions must be satis? ed for the duration of 100ms to ensure that any contact bounce during insertion has ended. when these initial conditions are satis? ed, the on pin is checked and its state written to bit a3 in table 2. if it is high, the external mosfet is turned on. if the on pin is low, the external mosfet is turned on when the on pin is brought high or if a serial bus turn-on command is sent by setting bit a3. the mosfet is turned on by charging up the gate with a 20a current source. when the gate voltage reaches the mosfet threshold voltage, the mosfet begins to turn on and the source voltage then follows the gate voltage as it increases. when the mosfet is turning on, it ramps inrush current up linearly at a di/dt rate selected by capacitor c ss . once the inrush current reaches the limit set by the fb pin, the figure 1. typical application + r3 3.4k 1% plug-in card r2 1.18k 1% r5 10 rs 0.005 q1 fdc653n r7 30.1k 1% v out 12v r8 3.57k 1% 4215 f01 c l 330f c f 0.1f connector 2 connector 1 r1 34.8k 1% backplane c3 0.1f c timer 0.68f gnd scl alert sda 12v r4 100k z1 p6ke16a r6 15k c1 6.8nf uv v dd sense + sense C ltc4215ufd gate adr1 adr2 adr0 timer intv cc gnd source ov on sdai sda0 scl alert fb adin gpio en ss c ss 7.5nf
ltc4215/ltc4215-2 13 4215fe applications information di/dt ramp stops and the inrush current follows the foldback pro? le as shown in figure 2. the timer pin integrates at 100a during start-up and once it reaches its threshold of 1.235v, the part checks to see if it is in current limit, which indicates that it has started up into a short-circuit condition. if this is the case, the overcurrent fault bit, d2 in table 5, is set and the part turns off. if the part is not in current limit, the 25mv circuit breaker is armed and the current limit is switched to 75mv. alternately an internal 100ms start-up timer may be selected by tying the timer pin to intv cc . as the source voltage rises, the fb pin follows as set by r7 and r8. once fb crosses its 1.235v threshold, and the start-up timer has expired, the gpio pin, in its default con? guration, ceases to pull low and indicates that power is now good. generates an oc fault, or the fb pin voltage crosses its 1.235v power good threshold and the gpio pin signals power good. gate pin voltage a curve of gate-to-source drive vs v dd is shown in the typical performance characteristics. at minimum input supply voltage of 2.9v, the minimum gate-to-source drive voltage is 4.7v. the gate-to-source voltage is clamped below 6.5v to protect the gates of logic level n-channel mosfets. turn-off sequence the gate is turned off by a variety of conditions. a normal turn-off is initiated by the on pin going low or a serial bus turn-off command. additionally, several fault conditions turn off the gate. these include an input overvoltage (ov pin), input undervoltage (uv pin), overcurrent circuit breaker (sense C pin), or en transitioning high. writing a logic one into the uv, ov or oc fault bits (d0-d2 in table 5) also latches off the gate if their auto-retry bits are set to false. normally the mosfet is turned off with a 1ma current pulling down the gate pin to ground. with the mosfet turned off, the source and fb voltages drop as c l dis- charges. when the fb voltage crosses below its threshold, gpio pulls low to indicate that the output power is no longer good. if the v dd pin falls below 2.74v for greater than 2s or intv cc drops below 2.60v for greater than 1s, a fast shut down of the mosfet is initiated. the gate pin is pulled down with a 450ma current to the source pin. overcurrent fault the ltc4215 features an adjustable current limit that protects against short circuits or excessive load current. an overcurrent fault occurs when the circuit breaker 25mv threshold has been exceeded for longer than the 20s (ltc4215) or 420s (ltc4215-2) time-out delay. current limiting begins immediately when the current sense voltage between the v dd and sense pins reaches 75mv. the gate v dd + 6v v gate v out gpio1 (power good) i load ? r sense v dd v sense 25mv 10mv ss limited fb limited 4215 f02 timer expires t startup figure 2. power-up waveforms if r6 and c1 are employed for a constant current during start-up, which produces a constant dv/dt at the output, a 20a pull-up current from the gate pin slews the gate upwards and the part is not in current limit. the start-up timer may expire in this condition and an oc fault is not generated even though start-up has not completed. either the sense voltage increases to the 25mv cb threshold and
ltc4215/ltc4215-2 14 4215fe applications information subsequently falls back below the threshold for 100ms, the gate is allowed to turn on again unless overvoltage auto-retry has been disabled by clearing bit a0. undervoltage fault an undervoltage fault occurs when the uv pin falls below its 1.235v threshold for more than 2s. this turns off the gate with a 1ma current to ground and sets undervoltage present bit c1 and undervoltage fault bit d1. if the uv pin subsequently rises above the threshold for 100ms, the gate is turned on again unless undervoltage auto-retry has been disabled by clearing bit a1. when power is applied to the device, if uv is below its 1.235v threshold after intv cc crosses its 2.64v undervoltage lockout threshold, an undervoltage fault is logged in the fault register. board present change of state whenever the en pin toggles, bit d4 is set to indicate a change of state. when the en pin goes high, indicating board removal, the gate turns off immediately (with a 1ma current to ground) and clears the board present bit, c4. if the en pin is pulled low, indicating a board insertion, all fault bits except d4 are cleared and enable bit, c4, is set. if the en pin remains low for 100ms the state of the on pin is captured in fet on control bit a3. this turns the switch on if the on pin is tied high. there is an internal 10a pull-up current source on the en pin. if the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. in cases where the ltc4215 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the en pin detects when the plug-in card is removed. figure 4 shows an example where the en pin is used to detect insertion. once the plug-in card is reinserted the fault register is cleared (except for d4). after 100ms the state of the on pin is latched into bit a3 of the control register. at this point the system starts up again. figure 3. short-circuit waveforms v gate 10v/div v source 10v/div v dd 10v/div i load 10a/div 5s/div 4215 f03 r s = 5m c l = 0 r short = 1 r6 = 30k c1 = 0.1f pin is then brought down and regulated in order to limit the current sense voltage to 75mv. when the 20s (ltc4215) or 420s (ltc4215-2) circuit breaker time out has expired, the overcurrent present bit c2 is set. the external mosfet is turned off and the overcurrent fault bit d2 is set. after the mosfet is turned off, the timer capacitor begins discharging with a 2a pulldown current. when the timer pin reaches its 0.2v threshold the mosfet is allowed to turn on again if the overcurrent fault has been cleared. however, if the overcurrent auto-retry bit, a2 has been set then the mosfet turns on again automatically without resetting the overcurrent fault. use a minimum value of 10nf for c t . if the timer pin is bypassed by tying it to intv cc , the part is allowed to turn on again after an internal 5 second timer has expired, in the same manner as the timer pin passing its 0.2v threshold. overvoltage fault an overvoltage fault occurs when either the ov pin rises above its 1.235v threshold, or the v dd pin rises above its 15.6v threshold, for more than 2s. this shuts off the gate with a 1ma current to ground and sets the overvoltage present bit c0 and the overvoltage fault bit d0. if the pin
ltc4215/ltc4215-2 15 4215fe applications information if a connection sense on the plug-in card is driving the en pin, insertion or removal of the card may cause the pin voltage to bounce. this results in clearing the fault register when the card is removed. the pin may be debounced using a ? lter capacitor, c en , on the en pin as shown in figure 4. the ? lter time is given by: t filter = c en ? 123 [ms/f] fault alerts when any of the fault bits in fault register d are set, an optional bus alert is generated if the appropriate bit in the alert register b has been set. this allows only selected faults to generate alerts. at power-up the default state is to not alert on faults. if an alert is enabled, the correspond- ing fault causes the alert pin to pull low. after the bus master controller broadcasts the alert response address, the ltc4215 responds with its address on the sda line and releases alert as shown in table 6. if there is a collision between two ltc4215s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds ? rst. the alert line is also released if the device is addressed by the bus master. once the alert signal has been released for one fault, it is not pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults do not generate alerts until the associ- ated fault register bit has been cleared. resetting faults faults are reset with any of the following conditions. first, a serial bus command writing zeros to the fault register d clears the associated faults. second, the entire fault register is cleared when the switch is turned off by the on pin or bit a3 going from high to low, if the uv pin is brought below its 0.4v reset threshold for 2s, or if intv cc falls below its 2.64v undervoltage lockout threshold. finally, when en is brought from high to low, only fault bits d0-d3 are cleared, and bit d4, that indicates a en change of state, is set. note that faults that are still present, as indicated in status register c, cannot be cleared. the fault register is not cleared when auto-retrying. when auto-retry is disabled the existence of a d0, d1 or d2 fault keeps the switch off. as soon as the fault is cleared, the switch turns on. if auto-retry is enabled, then a high value in c0, c1 or c2 holds the switch off and the fault register is ignored. subsequently, when bits c0, c1 C + 1.235v gnd motherboard connector plug-in card source out ltc4215 en c en load 4215 f04 10a figure 4. plug-in card insertion/removal fet short fault a fet short fault is reported if the data converter measures a current sense voltage greater than or equal to 1.6mv while the gate is turned off. this condition sets fet short present bit, c5, and fet short fault bit d5. power bad fault a power bad fault is reported if the fb pin voltage drops below its 1.235v threshold for more than 2s when the gate is high. this pulls the gpio pin low immediately when con? gured as power-good, and sets power-bad present bit, c3, and power bad fault bit d3. a circuit pre- vents power-bad faults if the gate-to-source voltage is low, eliminating false power-bad faults during power-up or power-down. if the fb pin voltage subsequently rises back above the threshold, the gpio pin returns to a high impedance state and bit c3 is reset.
ltc4215/ltc4215-2 16 4215fe applications information and c2 are cleared by removal of the fault condition, the switch is allowed to turn on again. the ltc4215 will set bit d2 and turn off in the event of an overcurrent fault, preventing it from remaining in an overcurrent condition. if con? gured to auto-retry, the ltc4215 will continually attempt to restart after cool-down cycles until it succeeds in starting up without generating an overcurrent fault. data converter the ltc4215 incorporates an 8-bit ? a/d converter that continuously monitors three different voltages. the ? architecture inherently averages signal noise during the measurement period. the source pin has a 1/12.5 resistive divider to monitor a full scale voltage of 15.4v with 60mv resolution. the adin pin is monitored with a 1.235v full scale and 4.82mv resolution, and the voltage between the v dd and sense pins is monitored with a 38.6mv full scale and 151v resolution. results from each conversion are stored in registers e (sense), f (source) and g (adin), as seen in tables 6-8, and are updated 10 times per second. setting control register bit a5 invokes a test mode that halts the data converter so that registers e, f, and g may be written to and read from for software testing. con? guring the gpio pin table 2 describes the possible states of the gpio pin using the control register bits a6 and a7. at power-up, the default state is for the gpio pin to go high impedance when power is good (fb pin greater than 1.235v). other applications for the gpio pin are to pull down when power is good, a general purpose output and a general purpose input. current limit stability for many applications the ltc4215 current limit will be stable without additional components. however there are certain conditions where additional components may be needed to improve stability. the dominant pole of the cur- rent limit circuit is set by the capacitance and resistance at the gate of the external mosfet, and larger gate capaci- tance makes the current limit loop more stable. usually a total of 8nf gate to source capacitance is suf? cient for stability and is typically provided by inherent mosfet c gs , however the stability of the loop is degraded by increasing r sense or by reducing the size of the resistor on a gate rc network if one is used, which may require additional gate to source capacitance. board level short-circuit testing in highly recommended as board layout can also affect transient performance, for stability testing the worst case condition for current limit stability occurs when the output is shorted to ground after a normal startup. there are two possible parasitic oscillations when the mosfet operates as a source follower when ramping at power-up or during current limiting. the ? rst type of oscillation occurs at high frequencies, typically above 1mhz. this high frequency oscillation is easily damped with r5 as shown in figure 1. in some applications, one may ? nd that r5 helps in short-circuit transient recovery as well. however, too large of an r5 value will slow down the turn-off time. the recommended r5 range is between 5 and 500. the second type of source follower oscillation occurs at frequencies between 200khz and 800khz due to the load capacitance being between 0.2f and 9f, the presence of r5 resistance, the absence of a drain bypass capacitor, a combination of bus wiring inductance and bus supply output impedance. to prevent this second type of oscillation avoid load capacitance below 10f, alternately connect an external capacitor from the mosfet gate to ground with a value greater than 1.5f. supply transients the ltc4215 is designed to ride through supply transients caused by load steps. if there is a shorted load and the parasitic inductance back to the supply is greater than 0.5h, there is a chance that the supply collapses before the active current limit circuit brings down the gate pin. if this occurs, the undervoltage monitors pull the gate
ltc4215/ltc4215-2 17 4215fe applications information pin low. the undervoltage lockout circuit has a 2s ? lter time after v dd drops below 2.74v. the uv pin reacts in 2s to shut the gate off, but it is recommended to add a ? lter capacitor c f to prevent unwanted shutdown caused by a transient. eventually either the uv pin or undervoltage lockout responds to bring the current under control before the supply completely collapses. supply transient protection the ltc4215 is safe from damage with supply voltages up to 24v. however, spikes above 24v may damage the part. during a short-circuit condition, large changes in current ? owing through power supply traces may cause inductive voltage spikes which exceed 24v. to minimize such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. also, a snubber circuit dampens inductive voltage spikes. build a snubber by using a 100 resistor in series with a 0.1f capacitor between v dd and gnd. a surge suppressor, z1 in figure 1, at the input can also prevent damage from voltage surges. design example as a design example, take the following speci? cations: v in = 12v, i max = 5a, i inrush = 1a, di/dt inrush = 10a/ms, c l = 330f, v uv(on) = 10.75v, v ov(off) = 14.0v, v pwrgd(up) = 11.6v, and i 2 c address = 1010011. this completed design is shown in figure 1. selection of the sense resistor, r s , is set by the overcurrent threshold of 25mv: r mv i s max == 25 0 005 . the mosfet is sized to handle the power dissipation dur- ing inrush when output capacitor c out is being charged. a method to determine power dissipation during inrush is based on the principle that: energy in cl = energy in q1 this uses: energy in c l == ()() 1 2 1 2 033 12 2 2 cv mf . or 0.024 joules. calculate the time it takes to charge up c out : tc v i mf v a ms startup l dd inrush == = ?.? 033 12 1 4 the power dissipated in the mosfet: p t w diss startup == energyin c l 6 the soa (safe operating area) curves of candidate mosfets must be evaluated to ensure that the heat capacity of the package tolerates 6w for 4ms. the soa curves of the fairchild fdc653n provide for 2a at 12v (24w) for 10ms, satisfying this requirement. since the fdc653n has less than 8f of gate capacitance and we are using a gate rc network, the short circuit stability of the current limit should be checked and improved by adding a capacitor from gate to source if needed. the inrush current is set to 1a using c1: cc i i cmf a a or c l gate inrush 1 1033 20 1 16 = == ? .???.8 8nf the inrush di/dt is set to 10a/ms using c ss : c i di dt a s r a ss ss sense = ? ? ? ? ? ? = / ?. ? 0 0375 1 10 100 0 00 0 0375 1 5 75 ?. ? . m nf =
ltc4215/ltc4215-2 18 4215fe applications information for a start-up time of 4ms with a 2x safety margin we choose: c t ms f c c ms timer startup ss timer =+ = 2 12 3 10 8 ? ./ ? 1 12 3 75 10 068 ./ .? . ms f nf f +? note the minimum value of c timer is 10nf, and each 1nf of soft-start capacitance needs 10nf of timer capaci- tance/time during start-up. the uv and ov resistor string values can be solved in the following method. first pick r3 based on i string being 1.235v/r3 at the edge of the ov rising threshold, where i string > 40a. then solve the following equations: r2 = v v ?r3? uv ov ov(off) uv(on) th(rising) t h h(falling) uv(on) th(ri Cr3 r1 = v uv ?( ) rr 32 + s sing) CC rr 32 in our case we choose r3 to be 3.4k to give a resistor string current below 100a. then solving the equations results in r2 = 1.16k and r1 = 34.6k. the fb divider is solved by picking r8 and solving for r7, choosing 3.57k for r8 we get: r7 = v fb pwrgd(up) th(rising) ? C r r 8 8 resulting in r7 = 30k. a 0.1f capacitor, c f , is placed on the uv pin to prevent supply glitches from turning off the gate via uv or ov. the address is set with the help of table 1, which indi- cates binary address 1010011 corresponds to address 19. address 19 is set by setting adr2 high, adr1 open and adr0 high. next the value of r5 and r6 are chosen to be the default values 10 and 15k as discussed previously. uv ov ss gnd on en sdao fb gpio intv cc timer adin adr2 adr1 v dd sense + sense C gate source sdai scl alert nc adr0 r2 r3 c f z1 r1 sense resistor r s c3 ltc4215ufd r8 i load 4215 f05 i load figure 5. recommended layout in addition a 0.1f ceramic bypass capacitor is placed on the intv cc pin. layout considerations to achieve accurate current sensing, a kelvin connection is required. the minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. using 0.03" per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 530 / ? . small resistances add up quickly in high current applications. to improve noise immunity, put the resistive dividers to the uv, ov and fb pins close to the device and keep traces to v dd and gnd short. it is also important to put the bypass capacitor for the intv cc pin, c3, as close as possible between intv cc and gnd. a 0.1f capacitor from the uv pin (and ov pin through resistor r2) to gnd also helps reject supply noise. figure 4 shows a layout that addresses these issues. note that a surge suppressor, z1, is placed between supply and ground using wide traces.
ltc4215/ltc4215-2 19 4215fe applications information scl sda start condition stop condition address r/ w ack data ack data ack 1 - 7 8 9 4215 f06 a6 - a0 b7 - b0 b7 - b0 1 - 7 8 9 1 - 7 8 9 p s figure 6. data transfer over i 2 c or smbus digital interface the ltc4215 communicates with a bus master using a 2-wire interface compatible with i 2 c bus and smbus, an i 2 c extension for low power devices. the ltc4215 is a read-write slave device and supports smbus bus read byte, write byte, read word and write word commands. the second word in a read word com- mand is identical to the ? rst word. the second word in a write word command is ignored. data formats for these commands are shown in figures 6 to 11. start and stop conditions when the bus is idle, both scl and sda are high. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high, as shown in figure 6. when the master has ? nished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. i 2 c device addressing twenty-seven distinct bus addresses are available using three 3-state address pins, adr0-adr2. table 1 shows the correspondence between pin states and addresses. note that address bits b7 and b6 are internally con? gured to 10. in addition, the ltc4215 responds to two special addresses. address (1011 111) is a mass write address that writes to all ltc4215s, regardless of their individual address settings. mass write can be disabled by setting register a4 to zero. address (0001 100) is the smbus alert response address. if the ltc4215 is pulling low on the alert pin, it acknowledges this address by broadcasting its address and releasing the alert pin. acknowledge the acknowledge signal is used in handshaking between transmitter and receiver to indicate that the last byte of data was received. the transmitter always releases the sda line during the acknowledge clock pulse. when the slave is the receiver, it pulls down the sda line so that it remains low during this pulse to acknowledge receipt of the data. if the slave fails to acknowledge by leaving sda high, then the master may abort the transmission by generating a stop condition. when the master is receiving data from the slave, the master pulls down the sda line during the clock pulse to indicate receipt of the data. after the last byte has been received the master leaves the sda line high (not acknowledge) and issues a stop condition to terminate the transmission. write protocol the master begins communication with a start con- dition followed by the seven bit slave address and the r/ w bit set to zero, as shown in figure 7. the addressed ltc4215 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. the ltc4215 acknowledges this and then latches the lower three bits of the command byte into its internal register address pointer. the master then delivers the data byte and the ltc4215 acknowledges once more and latches the data into its control register.
ltc4215/ltc4215-2 20 4215fe applications information s address 1 0 a4:a0 4215 f07 from master to slave from slave to master a: acknowledge (low) a : not acknowledge (high) r: read bit (high) w : write bit (low) s: start condition p: stop condition command data x x x x x b2:b0 0 w 000 b7:b0 a a ap figure 7. ltc4215 serial bus sda write byte protocol s address 1 0 a4:a0 command data data x x x x x b2:b0 0 w 000 0 4215 f08 x x x x x x x x b7:b0 a a a ap figure 8. ltc4215 serial bus sda write word protocol s address 1 0 a4:a0 1 0 a4:a0 1 0 command s address r a b7:b0 1 data x x x x x b2:b0 0 w 00 4215 f10 a a a p figure 9. ltc4215 serial bus sda read byte protocol s address 1 0 a4:a0 1 0 a4:a0 1 0 command s address r a b7:b0 1 data x x x x x b2:b0 0 w 00 4215 f11 a 0 a b7:b0 data a a p figure 10. ltc4215 serial bus sda read word protocol s alert response address 0 0 0 1 1 0 0 device address 1 0 a4:a0 0 1 1 r 0 4215 f11 a a p figure 11. ltc4215 serial bus sda alert response protocol the transmission is ended when the master sends a stop condition. if the master continues sending a second data byte, as in a write word command, the second data byte is acknowledged by the ltc4215 but ignored, as shown in figure 8. read protocol the master begins a read operation with a start condition followed by the seven bit slave address and the r/ w bit set to zero, as shown in figure 9. the addressed ltc4215 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to read. the ltc4215 acknowledges this and then latches the lower three bits of the command byte into its internal register address pointer. the master then sends a repeated start condition followed by the same seven bit address with the r/ w bit now set to one. the ltc4215 acknowledges and send the contents of the requested register. the transmission is ended when the master sends a stop condition. if the master acknowledges the transmitted data byte, as in a read word command, figure 10, the ltc4215 repeats the requested register as the second data byte.
ltc4215/ltc4215-2 21 4215fe applications information alert response protocol when any of the fault bits in fault register d are set, an optional bus alert is generated if the appropriate bit in the alert register b is also set. if an alert is enabled, the corresponding fault causes the alert pin to pull low. after the bus master controller broadcasts the alert response address, the ltc4215 responds with its address on the sda line and then release alert as shown in figure 11. the alert line is also released if the device is addressed by the bus master. the alert signal is not pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults do not generate alerts until the associated fault register bit has been cleared. table 1a. ltc4215 device addressing (uh24 package) description device address device address ltc4215uh address pins h 76543210adr2adr1adr0 mass write be 10111110xxx alert response 19 00011001xxx 0 80 1000000xlncl 1 82 1000001xlhnc 2 84 1000010xlncnc 3 86 1000011xlnch 4 88 1000100xlll 5 8a 1000101xlhh 6 8c 1000110xllnc 7 8e 1000111xllh 8 90 1001000xncncl 9 92 1001001xnchnc 10 94 1001010xncncnc 11 96 1001011xncnch 12 98 1001100xncll 13 9a 1001101xnchh 14 9c 1001110xnclnc 15 9e 1001111xnclh 16 a0 1010000xhncl 17 a2 1010001xhhnc 18 a4 1010010xhncnc 19 a6 1010011xhnch 20 a8 1010100xhll 21 aa 1010101xhhh 22 ac 1010110xhlnc 23 ae 1010111xhlh 24 b0 1011000xlhl 25 b2 1011001xnchl 26 b4 1011010xhhl
ltc4215/ltc4215-2 22 4215fe applications information table 1b. ltc4215 device addressing (gn16 package) description device address device address ltc4215gn address pins h 76543210adr2adr1adr0 mass write be 10111110xxx alert response 19 00011001xxx 0 90 1001000xncncl 1 94 1001010xncncnc 2 96 1001011xncnch table 2. control register a (00h)read/write bit name operation a7:6 gpio con? gure function a6 a7 gpio pin power good (default) 0 0 gpio = c3 power good 0 1 gpio = c3 general purpose output 1 0 gpio = b6 general purpose input 1 1 c6 = gpio a5 test mode enable enables test mode to disable the adc; 1 = adc disable, 0 = adc enable (default) a4 mass write enable allows mass write addressing; 1 = mass write enabled (default), 0 = mass write disabled a3 fet on control on control bit latches the state of the on pin at the end of the debounce delay; 1 = fet on, 0 = fet off a2 overcurrent auto-retry overcurrent auto-retry bit; 1 = auto-retry after overcurrent (default ltc4215-2), 0 = latch off after overcurrent (default ltc4215) a1 undervoltage auto-retry undervoltage auto-retry; 1 = auto-retry after undervoltage (default), 0 = latch off after undervoltage a0 overvoltage auto-retry overvoltage auto-retry; 1 = auto-retry after overvoltage (default), 0 = latch off after overvoltage table 3. alert register b (01h)read/write bit name operation b7 reserved not used b6 gpio output output data bit to gpio pin when con? gured as output. defaults to 0 b5 fet short alert enables alert for fet short condition; 1 = enable alert, 0 = disable alert (default) b4 en state change alert enables alert when en changes state; 1 = enable alert, 0 disable alert (default) b3 power bad alert enables alert when output power is bad; 1 = enable alert, 0 disable alert (default) b2 overcurrent alert enables alert for overcurrent condition; 1 = enable alert, 0 disable alert (default) b1 undervoltage alert enables alert for undervoltage condition; 1 = enable alert, 0 disable alert (default) b0 overvoltage alert enables alert for overvoltage condition; 1 = enable alert, 0 disable alert (default)
ltc4215/ltc4215-2 23 4215fe applications information table 4. status register c (02h)read bit name operation c7 fet on 1 = fet on, 0 = fet off c6 gpio input state of the gpio pin; 1 = gpio high, 0 = gpio low c5 fet short present indicates potential fet short if current sense voltage exceeds 1mv while fet is off; 1 = fet is shorted, 0 = fet is not shorted c4 en indicates if the ltc4215 is enabled when en is low; 1 = en pin low, 0 = en pin high c3 power bad indicates power is bad when fb is low; 1 = fb low, 0 = fb high c2 overcurrent indicates overcurrent condition during cool down cycle; 1 = overcurrent, 0 = not overcurrent c1 undervoltage indicates input undervoltage when uv is low; 1 = uv low, 0 = uv high c0 overvoltage indicates v dd or ov input overvoltage when ov is high; 1 = ov high, 0 = ov low table 5. fault register d (03h)read/write bit name operation d7:6 reserved d5 fet short fault occurred indicates potential fet short was detected when measured current sense voltage exceeded 1mv while fet was off; 1 = fet is shorted, 0 = fet is good d4 en changed state indicates that the ltc4215 was enabled or disabled when en changed state; 1 = en changed state, 0 = en unchanged d3 power bad fault occurred indicates power was bad when fb when low; 1 = fb was low, 0 = fb was high d2 overcurrent fault occurred indicates overcurrent fault occurred; 1 = overcurrent fault occurred, 0 = not overcurrent faults d1 undervoltage fault occurred indicates input undervoltage fault occurred when uv went low; 1 = uv was low, 0 = uv was high d0 overvoltage fault occurred indicates input overvoltage fault occurred when ov went high; 1 = ov was high, 0 = ov was low table 6. sense register e (04h)read/write bit name operation e7:0 sense voltage measurement sense voltage data. 8-bit data with 151v lsb and 38.45mv full scale. table 7. source register f (05h)read/write bit name operation f7:0 source voltage measurement source voltage data. 8-bit data with 60.5mv lsb and 15.44v full scale. table 8. adin register g (06h)read/write* bit name operation g7:0 adin voltage measurement adin voltage data. 8-bit data with 4.82mv lsb and 1.23v full scale. *the adin pin is not available in the gn16 package.
ltc4215/ltc4215-2 24 4215fe typical applications + uv v dd sense C ltc4215gn gate intv cc timer gnd adr0 source sda scl alert on fb gpio ss plug-in card r5 10 r6 15k c1 22nf c ss 68nf r s 0.0015 q1 si7880dp r7 30.1k 1% r8 3.57k 1% r4 100k 4215 f12 c l 1000f c f 0.1f 15v r1 34.8k 1% r2 4.42k 1% backplane gnd alert scl sda v in 12v c timer 1f c3 0.1f z1 p6ke16a 12v card resident application with a 16.6a circuit breaker
ltc4215/ltc4215-2 25 4215fe typical applications 5v backplane resident application with insertion activated turn-on and a 5a circuit breaker uv v dd sense + sense C ltc4215ufd gate intv cc timer adr0 adr1 adr2 gnd source ov on sdai sdao scl alert fb gpio en adin ss r3 2.67k 1% plug-in card r2 1.74k 1% r5 10 r s 0.005 q1 fdd3706 r7 6.98k 1% v out 5v r8 2.67k 1% r4 100k 4215 f13 c f 0.1f c3 0.1f r1 11.5k 1% v in 5v backplane c en 1f c ss 68nf load
ltc4215/ltc4215-2 26 4215fe package description gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 p .004 (0.38 p 0.10) s 45 o 0 o C 8 o typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 p .0015 .045 p .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
ltc4215/ltc4215-2 27 4215fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 4.00 p 0.10 (2 sides) 5.00 p 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 23 24 1 2 bottom viewexposed pad 0.75 p 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or c = 0.35 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd24) qfn 0506 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 0.25 p 0.05 0.50 bsc 2.65 p 0.05 2.00 ref 3.00 ref 4.10 p 0.05 5.50 p 0.05 3.10 p 0.05 4.50 p 0.05 package outline 2.65 p 0.10 2.00 ref 3.00 ref 3.65 p 0.10 3.65 p 0.05 ufd package 24-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1696 rev a)
ltc4215/ltc4215-2 28 4215fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0709 rev e ? printed in usa related parts typical application part number description comments ltc1421 dual channel, hot swap controller operates from 3v to 12v, supports C12v, ssop-24 ltc1422 single channel, hot swap controller operates from 2.7v to 12v, so-8 ltc1642a single channel, hot swap controller operates from 3v to 16.5v, overvoltage protection up to 33v, ssop-16 ltc1645 dual channel, hot swap controller operates from 3v to 12v, power sequencing, so-8 or so-14 ltc1647-1/ltc1647-2/ ltc1647-3 dual channel, hot swap controller operates from 2.7v to 16.5v, so-8 or ssop-16 ltc4151 high voltage current and voltage monitor with adc and i 2 c 7v to 80v single voltage/current monitor with 12-bit adc ltc4210 single channel, hot swap controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4211 single channel, hot swap controller operates from 2.5v to 16.5v, multifunction current control, msop-8 or msop-10 ltc4212 single channel, hot swap controller operates from 2.5v to 16.5v, power-up timeout, msop-10 ltc4216 single channel, hot swap controller operates from 0v to 6v, msop-10 or 12-lead (4mm 3mm) dfn ltc4222 dual hot swap controller with adc and i 2 c 2.9v to 29v dual controller with 10-bit adc, dl/dt controlled soft-start ltc4245 multiple supply compactpci or pci express hot swap controller with i 2 c internal 8-bit adc, dl/dt controlled soft-start ltc4260 positive high voltage hot swap controller with adc and i 2 c 8-bit adc monitoring current and voltages, supplies from 8.5v to 80v ltc4261 negative high voltage hot swap controller with adc and i 2 c 10-bit adc monitoring current and voltages, supplies from C12v to C100v uv v dd sense + sense C ltc4215ufd gate intv cc adr0 adr1 adr2 gnd source ov sdai sdao scl on fb adin gpio en ss timer r5 10 r6 15k c1 22nf r s 0.0015 q1 si7880dp C12v r7 30.1k 1% output C12v r8 3.57k 1% 4215 f14 c3 0.1f d1 5.6v r14 100k r1 34.8k 1% r2 1.18k 1% r12 10k r4 3.3k r9 10k r10 3.3k C12v r3 3.4k 1% c timer 1f c f 0.1f c ss 68nf c l 1000f r13 3.3k hcpl-0300 28 C7v 3 6 5 hcpl-0300 28 C7v 3 6 5 C7v C7v C7v hcpl-0300 68 5 2 3 C7v q2 plug-in card backplane gnd 5v sda scl v in C12v d2 p6ke16a C12v card resident application with optically isolated i 2 c and a 16.6a circuit breaker

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